1. Field of the Invention:
This invention relates to semiconductor integrated circuit devices and in particular to Complementary Metal Oxide Semiconductor field effect transistors (hereinafter referred to by the abbreviation CMOS) in which difficulties caused by parasitic bipolar transistors are eliminated.
2. Description of the Prior Art:
Various CMOS circuits have been known in the past, and a typical example of these is a CMOS inverter circuit. This inverter circuit is made up of a P channel type MOS transistor Q.sub.1 and an N channel type MOS transistor Q.sub.2 ; the source electrode of the transistor Q.sub.1 is connected to a positive power source V.sub.DD ; the drain electrode of the transistor Q.sub.1 and the drain electrode of the transistor Q.sub.2 are connected together and both are connected to an output terminal OUT, and the source electrode of the transistor Q.sub.2 is connected to a negative power source V.sub.SS. Also, the gate electrodes of the transistors Q.sub.1 and Q.sub.2 are both connected to an input terminal IN to make up an inverter.
In a CMOS circuit constructed in this manner, the threshold direct voltages V.sub.th of the N and P channel MOS transistors have opposite polarities, and therefore their actions on input voltages are entirely opposite to one another, and the operating power is extremely small. For example, if the power source V.sub.DD is made +5 V and the power souce V.sub.SS is made earth (GND), and if +5 V is supplied to the input IN, the transistor Q.sub.2 conducts and the transistor Q.sub.1 does not conduct, and no direct current at all flows between the power sources V.sub.DD and V.sub.SS. Conversely, if zero V is supplied to the input IN, the transistor Q.sub.2 becomes non-conductive and the transistor Q.sub.1 becomes conductive, and once again direct current does not flow between the power sources V.sub.DD and V.sub.SS. Therefore, in the CMOS circuit there is generally practically no operating power consumption; in the input information pulse transition time region, the transistors Q.sub.1 and Q.sub.2 both conduct, and all that happens is that an instantaneous transition current flows along with leakage current occurring at the PN junctions, and the current due to the charge and discharge of the load capacity at the output. Accordingly, in general the power of CMOS circuits can be said to be extremely small.
But in CMOS circuit systems of this kind, when noise in the form of an impulse is applied to the output or to the input, a large direct current (several dozen mA to several hundred mA) flows between the power sources V.sub.DD and V.sub.SS, and even when this noise is stopped, a phenomenon occurs whereby the large current continues to be maintained steadily. This phenomenon (hereinafter referred to as "Latch-up") magnifies the power consumption, and leads to a CMOS circuit of low reliability. The polarity of this impulse can be positive or negative; in order to eliminate this phenomenon it is necessary to reduce the power souce V.sub.DD below a certain voltage, or to cut off the power sources of the circuit system.